The present invention relates to an ESD protection device working in high voltage and the manufacturing method, more particularly to the ESD protection circuit, which comprises at least one PNP transistor and at least one diode coupled in parallel to enhance the ESD protection capability.
Electrostatic discharge (ESD) is the major threat to destroy an electrical element due to the electrical overstress (EOS) when the electrical element is operated. The ESD event can easily break down the electrical element and cause the semiconductor elements, computer system, etc. to be permanent damage since the elements are getting tiny and subtle. After that, the relevant product will be affected and failed.
The electrostatic charges will be accumulated in human body, electrical apparatus, or any other equipment during the electrical elements or device is under manufacturing, producing, installing, testing, storing or moving process. Generally, the electrostatic discharging is incurred from the cause of human body terminal. Afterward, the electrostatic charges will be discharged and formed an ESD discharging path while the human body terminals with the objects mentioned above or any other terminal event occurs between the elements. Then the electrical elements or devices would suffer the unexpected damage.
An ESD protection circuit or protection device is incorporated to be the discharging path provider within the integrated chip (IC) or electrical circuit generally. Since the elements used in the ESD protection circuit must have low breakdown voltage therein or- faster discharging speed, the ESD protection circuit nearby should have an ESD discharging path to discharge the ESD current at an early time while the ESD event occurred in the I/O pins.
The elements used in the ESD protection circuit of the prior art includes (1) Electric resistance; (2) Diode formed with PN junction; (3) NMOS/PMOS; (4) Field-oxide device; (5) Bipolar junction transistor; (6) Silicon controlled rectifier (SCR) device (P-N-P-N structure), etc.
FIG. 1 shows the current-voltage (I-V) curve of the ESD protection element. ESD protection element is used to discharge the ESD current in a first breakdown zone 2 shown in FIG. 1. If the ESD current reaches the second breakdown zone 4, the element would incur the permanent damage. In general, an ESD protection element can tolerate a maximum .ESD current Ibd, which is the current corresponding to a second breakdown point C shown in FIG. 1. When the element goes through a first breakdown point A to the second breakdown zone 4, the ESD protection device operates in a snap breakdown zone 3. Therefore, the ESD protection device will not be damaged, and even form an ESD discharging path to ground potential.
Reference is made to FIG. 2 shown an ESD protection device of the prior art. Two clamping diodes 25, 26 are installed between an input contact 21 and an inner circuit 23, and are used to be the protection devices as the ESD event occurred. When the input contact 21 received a positive ESD pulse, whose peak is higher than VDD, diode 25 will be turned on and induce current to flow to the power supply VDD rather than to the inner circuit 23. Similarly, when the input contact 21 received a negative ESD pulse, whose peak is lower than VSS, diode 26 will be turned on and induce current to flow to the power supply VSS rather than to the inner circuit 23.
U.S. Pat. No. 6,542,346 discloses an ESD protection circuit shown in FIG. 3. The ESD protection circuit is employed to couple with an input 31 and an inner circuit 33. The ESD protection circuit comprises a voltage-sharing- circuit 35 and a silicon controlled rectifier (SCR) 37. The voltage-sharing circuit 35 is electrically coupled between the VSS and the input 31, and a reference voltage not higher than the voltage of the input 31 is generated thereby. The SCR 37 electrically couples with the input 31, ground and the voltage-sharing circuit 35, and is formed by the heavily concentration P-type and N-type semiconductor. material on a P-type semiconductor substrate. Then the voltage-sharing circuit 35 is used to turn on a NMOS switch 36 of the SCR 37 by taking the reference of the reference voltage during the ESD discharging event. Wherein the NMOS switch 36 comprises a gate to trigger the SCR 37 to release the ESD current at input 31. Lastly the SCR 37 is to provide an ESD discharging path to protect the inner circuit 33.
A PNP transistor is to be the ESD protection element as the U.S. Pub. US2004/0085691A1 disclosed. Referring to FIG. 4, the ESD protection element comprises a P-type semiconductor substrate 40 to be the collector, a N-type well 42 is buried thereon, then the heavily concentration P-type semiconductor zones 401 402 are doped on the substrate 40, which is used to- be the terminals outside. An emitter of the ESD protection element is formed with the heavily concentration P-type semiconductor zone 403 doped within the N-type well 42. According to the structure, N-type heavily doped regions 411 and 412 are formed adjacent to the N-type well 42, and further a plurality of isolated layers 44 are formed to isolate the regions 401, 411, 403, 412 and 402. The structure stated above is equivalent to a PNP bipolar junction transistor with low breakdown voltage, and is formed the protection element. When the PN or NP junction avalanches due to the ESD discharging, the ESD discharging path is provided from the emitter formed by P-type semiconductor zone 403 to the collector formed by P-type semiconductor substrate 40 instantaneously.
Moreover, the junction between P-type semiconductor zone 403 and N-type well 42 has low breakdown voltage since the zone 403 is heavily doped. Otherwise, the junction between N-type well 42 and P-type semiconductor substrate 40 has a relatively high breakdown voltage since both the substrate 40 and the N-type well are lightly doped, and where the junction is not easily broken through by ESD current.
In view of the structure of the arts aforementioned has the capability of preventing the damage from ESD event, the present invention further provides an ESD protection device by electrically coupling diode and PNP transistor in parallel, and the strength of protection will be enhanced substantially, especially in human body mode. Specifically, the high-voltage ESD protection the present invention can meet is at least more than 4 KV.